VLSI implementation of LDPC decoder suited for OFDM applications

----Project Proposal(EECE 585)

September 27, 2005

Group members: Yi Wang(yxw4316@cacs.louisiana.edu)and Unni Chandran(uxc0983@cacs.louisiana.edu)

Project Supervisors:

Abu Baker

Yijun Li

Background:

One of the ambitious design goals of future wireless systems, including 4G, IEEE 802.11n/802.16 standards, is to reliably provide very high data rate transmission in hostile environments: hundred(s) of Mb/s or more for downlink transmission with a low frame error rate (FER), typically less than 5.10^-4 [3] Therefore, efficient decoders are required in order to mitigate inter-symbol-interface (ISI) and residual interference, respectively. It has been observed that Orthogonal Frequency Division Multiplexing (OFDM) modulation is particularly suited for transmissions over multi-path channels [3]. But, since the frequency selectivity implies that some sub-bands are strongly weakened, powerful receiver is needed. That’s why, these days several methods such as power allocation [1] or channel coding [4] have been used.

Since channel coding, for instance, Low-Density-Parity Check (LDPC) codes has been demonstrated to achieve information rates very close to the Shannon limit when iteratively decoded and in general, LDPC decoders are known to require an order of magnitude less arithmetic computations than Turbo decoders that provide similar bit-error performance. However, among the different existing codes, Low Density Parity-Check (LDPC) code presents a great interest for Coded OFDM (COFDM) transmission.

Therefore, we would like to realize VLSI implementation for LDPC decoder that will be suited for COFDM transmission of the future wireless standard.

Project Description:

According to the course requirements of EECE585, besides taking the limited design period into consideration, we will not cover all the topics of the whole LDPC Decoder system design. Instead, we will focus our work on the implementation of the two basic building blocks of a LDPC Decoder, namely, the check to variable processing element design and the variable to check processing element. By following a Down-to-Top design process, we wish the contributions to the whole system performance based on our efforts to improve the performance of these building blocks.

To make the design progress controllable, we partitioned the project into the following steps:

1. Preparing the layouts of adder cells with different type, Comparing the critical parameters of these cells so that we can make an optimized choice with respect to the Power, Delay, Area Occupation requirements of a LDPC Decoder applied to Coded OFDM (COFDM) transmission.

2. Analyzing the existing architectures of adder tree, find out suitable architectures and make the layouts. Evaluate the performance of the candidates, and then make the choice.

3. Combining the effort of both the system architecture design and the memory design, design the architecture of the processing elements. Meanwhile, taking the requirements the system interconnection into consideration, prepare the system floor-plan and modify the architecture of the processing elements in order to release the pressure of system interconnection. Evaluate the performance of the processing elements.

4. Complete the system interconnection, evaluate the system performance.

5. Given the time, take other considerations such as clock distribution, I/O design, and design for testability, then modify the design.

1] J.A.C. Bingham. Multicarrier modulation for data transmission: an idea whose time has come. Communications Magazine, IEEE, 28(5):5 – 14, May 1990.

[2] IEEE Std 802.16-2004 Revision of IEEE Std 802.16-2001. IEEE standard for local and metropolitan area networks part 16: Air interface for fixed broadband wireless access systems. Technical report, IEEE, 2004.

[3] S.J. Vaughan-Nichols. Achieving wireless broadband with WiMax. Computer, 37(6):10 – 13, June 2004.

[4] W.Y. Zou and Wu Yiyan. COFDM: an overview. Broadcasting, IEEE Transactions on, 41(1):1 – 8, March 1995.